In the prior art, inventors' prior art, “System and Method for Correcting Gate-level Simulation Accuracy when Unknowns Exist,” U.S. Pat. No. 8,402,405, a method for identifying false Xs and generating fixes was disclosed, and a methodology to correct gate-level simulation was proposed.
In the prior art, the system and method to identify false Xs work as follows. The input to the method is a register data input, d, that has X in logic simulation. The method returns true if the X is false; otherwise, false is returned. The fan-in cone circuit is also returned in subckt. This is achieved using the following steps.
(1) Trace the fan-in cone of d along the variables whose logic simulation values are Xs. Add all the gates along the trace to subckt. Stop when the variable is a primary input of the design or an output of a register.
(2) Build a Boolean function from subckt. The output of the function is d, and the inputs are the primary inputs of subckt. For each input, check its logic simulation value. If the value is not X, propagate the non-X value through the input to simplify the Boolean function. If the value is X, the input remains an input of the simplified Boolean function.
(3) Use a Boolean solver to check whether the output is constant. If so, return true. Otherwise, return false. subckt is also returned.
After false X is identified, our prior art minimizes X-eliminating sub-circuit to generate compact fixes to eliminate the false X. The input to the method is subckt, and the output is a new subckt that is a subset of the original one and still eliminates false Xs. The first minimization is called function ckt_minimize1 in our prior art and works as follows.
(1) Move the output of subckt to one of the inputs of its fan-in gate that has X in logic simulation. A new sub-circuit, subcktn, will be formed.
(2) Use the false-X identification algorithm described earlier to prove whether subcktn produces a false X and its output is still a constant. If it is no longer a constant, discard the change. Otherwise, replace subckt with subcktn. Repeat step (1) and (2) until no further changes can be made.
At this point, the primary output of subckt, called cpo, is a variable whose X is false that is farthest from the output of the original subckt. Function ckt_minimize2 in our prior art then performs the following steps that reduces subckt from its inputs. Note that we use terminology fanin frontier to represent a collection of wires in the netlist that form a cut while the logic on the fanout side of the cut still generates a false X.
(1) Remove each gate that connects to the primary inputs of subckt, one at a time, to form a new sub-circuit called subcktn. The output of the gate becomes a potential new fanin frontier variable.
(2) Check if cpo is still constant using subcktn. If it is no longer constant, discard the change. Otherwise, replace subckt with subcktn. Repeat step (1) and (2) until no further changes can be made.
At this point, subckt is a subset of the original subckt whose inputs are real Xs and whose output is a false X. Since removing any single gate will produce a real X again, this sub-circuit is a minimal one that can eliminate the X.
The sub-circuit (subckt) produced in the above method can be used to generate auxiliary-code to repair gate-level logic simulation, and the steps to do so are as follows.
(1) Traverse the inputs (fanin frontier) of subckt to generate the condition for the false X to occur based on its logic simulation value. For example, if variable var1 is 1 and var2 is X in logic simulation, the condition is “var1===1′b1 && var2===1′bx”.
(2) Generate code to replace the X with the known constant value when the condition matches. The constant value can be derived by assigning random non-X values to the inputs of subckt and checking its output. When the condition does not match, the generated code should disable such value over-write. In the Verilog and SystemVerilog Hardware Design Language, “force” and “release” commands can be used.
An example to repair the X-pessimism problem in the netlist shown in FIG. 1 is shown in FIG. 2. The generated code can fix all false Xs that match the condition.
Function ckt_minimize2 described in our prior art is based on a trial-and-error heuristic that iteratively removes each gate and then uses formal analysis to prove if the remaining subckt still generates a false X. While effective in producing highly optimized fixes, it is time-consuming and may not scale well to complicated logic with a large number of gates. This is especially problematic for arithmetic logic or design for testability constructs like observability or controllability points whose logic can be much more complicated than ordinary logic. In this invention we propose a new method to address this issue.